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Preliminary Technical Data
FEATURES Performance
* * * * * * *
DSP Microcomputer ADSP-2188M
12.5 ns Instruction Cycle Time @ 2.5 Volts (internal), 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Powerdown Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from Powerdown Condition Low Power Dissipation in Idle Mode
Integration
* * * * * * * *
ADSP-2100 Family Code Compatible (easy to use algebraic syntax), with Instruction Set Extensions 256K Bytes of On-Chip RAM, Configured as 48K Words On-Chip Program Memory RAM and 56K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, & Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP
System Interface
* * * * * * * * * * * * *
Flexible I/O structure allows 2.5V or 3.3V operation; all inputs tolerate up to 3.6V regardless of mode 16-Bit Internal DMA Port for High Speed Access to on-Chip Memory (Mode Selectable) 4 MByte Memory Interface for Storage of Data Tables & Program Overlays (Mode Selectable) 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe & Separate I/O Memory Space Permits "Glueless" System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-PortTM Emulator Interface Supports Debugging in Final Systems
Y R A IN AL IM IC LN EH RC A PE T T DA
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One Technology Way P.O. Box 9106 Norwood MA 02062-9106 U.S.A.
http://www.analog.com/dsp Tel: 1-800-ANALOG-D Fax: 1-781-461-3010 (c)Analog Devices Inc., 1999
April 1999
General note
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
This data sheet represents preliminary (x- grade) specifications for the ADSP-2188M 2.5V processor.
GENERAL DESCRIPTION
The ADSP-2188M is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2188M combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP-2188M integrates 256K bytes of on-chip memory configured as 48K words (24-bit) of program RAM, and 56K words (16-bit) of data RAM. Power down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2188M is available in a 100pin LQFP package. In addition, the ADSP-2188M supports new instructions, which include bit manipulations--bit set, bit clear, bit toggle, bit test--new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers, and global interrupt masking, for increased flexibility. Fabricated in a high speed, low power, CMOS process, the ADSP-2188M operates with a 13.3 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2188M's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSP-2188M can:
* * * * *
Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation Receive and transmit data through the two serial ports Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Decrement timer
This takes place while the processor continues to:
* * * *
DEVELOPMENT SYSTEM
The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2188M. The System Builder provides a high level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment.
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ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation's GNU C Compiler, generates ADSP-2188M assembly source code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions. The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the entire ADSP-21xx family: an ADSP-218x based evaluation board with PC monitor software plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features:
* * * * *
33 MHz ADSP-218x Full 16-bit Stereo Audio I/O with AD1847 SoundPort(R) Codec RS-232 Interface to PC with Windows 3.1 Control Software EZ-ICE Connector for Emulator Control DSP Demo Programs
The ADSP-218x EZ-ICE(R) Emulator aids in the hardware debugging of an ADSP-2188M system. The emulator consists of hardware, host computer resident software, and the target board connector. The ADSP-2188M integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-2188M device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. The EZ-ICE performs a full range of functions, including:
* * * * * * * *
In-target operation Up to 20 breakpoints Single-step or full-speed operation Registers and memory values can be examined and altered PC upload and download functions Instruction-level emulation of program booting and execution Complete assembly and disassembly of instructions C source-level debugging
See "Designing An EZ-ICE-Compatible Target System" in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as well as the "Designing an EZ-ICE compatible System" section of this data sheet for the exact specifications of the EZ-ICE target board connector.
Additional Information
This data sheet provides a general overview of ADSP-2188M functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User's Manual. For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.
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April 1999 ARCHITECTURE OVERVIEW
ADSP-2188M Preliminary Data Sheet
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The ADSP-2188M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2188M assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.
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Figure 1 FUNCTIONAL BLOCK DIAGRAM Figure 1 is an overall block diagram of the ADSP-2188M. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multi-word and block floating-point representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2188M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one
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ADSP-2188M Preliminary Data Sheet
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April 1999
of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses:
* * * * *
Program Memory Address (PMA) Bus Program Memory Data (PMD) Bus Data Memory Address (DMA) Bus Data Memory Data (DMD) Bus Result (R) Bus
The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSP-2188M to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2188M can fetch an operand from program memory and the next instruction in the same cycle. In lieu of the address and data bus for external memory connection, the ADSP-2188M may be configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM. An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-2188M to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSP-2188M can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal.The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSP-2188M provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, there are eight flags that are programmable as inputs or outputs, and three flags that are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycles, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).
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April 1999 Serial Ports
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
The ADSP-2188M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2188M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User's Manual.
* * *
* * * * *
SPORTs are bidirectional and have a separate, double-buffered transmit and receive section. SPORTs can use an external serial clock or generate their own serial clock internally. SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulse widths and timings. SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and -law companding according to CCITT recommendation G.711. SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, timedivision multiplexed, serial bitstream. SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration.
Pin Descriptions
The ADSP-2188M will be available in a 100-lead LQFP package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
Common Mode Pins
Pin Name(s) RESET BR BG BGH DMS PMS IOMS # of Pins 1 1 1 1 1 1 1 I/O I I O O O O O Function Processor Reset Input Bus Request Input Bus Grant Output Bus Grant Hung Output Data Memory Select Output Program Memory Select Output Memory Select Output
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Common Mode Pins (Continued)
Pin Name(s) BMS CMS RD WR IRQ2 PF7 IRQL0 PF6 IRQL1 PF5 IRQE PF4 Mode D PF3 Mode C PF2 Mode B PF1 Mode A PF0 CLKIN XTAL CLKOUT SPORT0 SPORT1 IRQ1:0, FI, FO PWD PWDACK FL0, FL1, FL2 VDDINT # of Pins 1 1 1 1 1 1 1 1 1 1 1 1 2 1 5 5 1 1 3 2 I/O O O O O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I O I/O I/O I O O I Function Byte Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Write Enable Output Edge- or Level-Sensitive Interrupt Request1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Edge-Sensitive Interrupt Requests1 Programmable I/O Pin Mode Select Input - Checked only coming out of RESET Programmable I/O Pin during normal operation Mode Select Input - Checked only coming out of RESET Programmable I/O Pin during normal operation Mode Select Input - Checked only coming out of RESET Programmable I/O Pin during normal operation Mode Select Input - Checked only coming out of RESET Programmable I/O Pin during normal operation Clock or Quartz Crystal Input Processor Clock Output Serial Port I/O Pins Serial Port I/O Pins Edge- or Level-Sensitive Interrupts, Flag In, Flag Out2 Powerdown Control Input Powerdown Control Output Output Flags Internal VDD (2.5V) Power
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April 1999 Common Mode Pins (Continued)
Pin Name(s) VDDEXT GND EZ-Port # of Pins 4 10 9 I/O I I I/O Function
ADSP-2188M Preliminary Data Sheet
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External VDD (2.5V or 3.3V) Power Ground For emulation use
1. Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2. SPORT configuration determined by the DSP System Control Register. Software configurable
Memory Interface Pins
The ADSP-2188M processor can be used in one of two modes, Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running.
Full Memory Mode Pins (Mode C = 0)
Pin Name A13:0 D23:0 # of Pins 14 24 I/O O I/O Function Address Output Pins for Program, Data, Byte and I/O Spaces Data I/O Pins for Program, Data, Byte and I/O Spaces (8 MSBs are also used as Byte Memory addresses)
Host Mode Pins (Mode C = 1)
Pin Name IAD15:0 A0 D23:8 IWR IRD IAL IS IACK # of Pins 16 1 16 1 1 1 1 1 I/O I/O O I/O I I I I O Function IDMA Port Address/Data Bus Address Pin for External I/O, Program, Data, or Byte access1 Data I/O Pins for Program, Data Byte and I/O spaces IDMA Write Enable IDMA Read Enable IDMA Address Latch Pin IDMA Select IDMA Port Acknowledge Configurable in Mode D; Open Drain
1. In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals
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Interrupts
The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. The ADSP-2188M provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six external interrupts. The ADSP-2188M also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software, and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge sensitive. The priorities and vector addresses of all interrupts are shown in Table 1. Table 1 Interrupt Priority & Interrupt Vector Addresses
Source Of Interrupt Reset (or Power-Up with PUCR = 1) Power Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer Interrupt Vector Address (Hex) 0000 (Highest Priority) 002C 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 (Lowest Priority)
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. The ADSP-2188M masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive interrupts. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global
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April 1999
ADSP-2188M Preliminary Data Sheet
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enable or disable servicing of the interrupts (including power down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA.
ENA INTS; DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2188M has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are:
* * *
Power Down Idle Slow Idle
The CLKOUT pin may also be disabled to reduce external power dissipation.
Power Down
The ADSP-2188M processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. Here is a brief list of power-down features. Refer to the ADSP-2100 Family User's Manual, "System Interface" chapter, for detailed information about the power-down feature.
* *
*
*
* * *
Quick recovery from power down. The processor begins executing instructions in as few as 200 CLKIN cycles. Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power down without affecting the lowest power rating and 200 CLKIN cycle recovery. Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 CLKIN cycle start up. Power down is initiated by either the power down pin (PWD) or the software power-down force bit.Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power down interrupt also can be used as a non-maskable, edge sensitive interrupt. Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power down state. The RESET pin also can be used to terminate power down. Power down acknowledge pin indicates when the processor has entered power down.
Idle
When the ADSP-2188M is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur.
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Slow Idle
The IDLE instruction is enhanced on the ADSP-2188M to let the processor's internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor's other internal clock signals, such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the processor's internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2188M will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor's reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the ADSP-2188M, two serial devices, a bytewide EPROM, and optional external program and data overlay memories (mode selectable). Programmable wait state generation allows the processor connects easily to slow peripheral devices. The ADSP-2188M also provides four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to
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April 1999
ADSP-2188M Preliminary Data Sheet
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a single address bit (A0). Additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals.
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Figure 2 ADSP-2188M Basic System Interface
Clock Signals
The ADSP-2188M can be clocked by either a crystal or by a TTL-compatible clock signal. The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal operation. The only exception is while the processor is in the power down state. For additional information, refer to Chapter 9, ADSP-2100 Family User's Manual for detailed information on this power down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor's CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSP-2188M uses an input clock with a frequency equal to half the instruction rate; a 37.50 MHz input clock yields a 13.3 ns processor cycle (which is equivalent to 75 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because the ADSP-2188M includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.
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A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register.
C L K IN
X T AL
C LK OU T
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Figure 3 External Crystal Connections
Reset
The RESET signal initiates a master reset of the ADSP-2188M. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse width specification, tRSP. The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.
Power Supplies
The ADSP-2188M has separate power supply connections for the internal (V DDINT) and external (VDDEXT) power supplies. The internal supply must meet the 2.5V requirement. The external supply can be connected to either a 2.5V or 3.3V supply. All external supply pins must be connected to the same supply. All input and I/O pins can tolerate input voltages up to 3.6V regardless of the external supply voltage. This feature provides maximum flexibility in mixing 2.5V and 3.3 volt components.
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April 1999 MODES OF OPERATION Setting Memory Mode
ADSP-2188M Preliminary Data Sheet
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Memory Mode selection for the ADSP-2188M is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP's PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive. Passive configuration involves the use a pull-up or pull-down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down, on the order of 100 k, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor's output driver. For minimum power consumption during powerdown, reconfigure PF2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. Active configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver's output enable should be connected to the DSP's RESET signal such that it only drives the PF2 pin when RESET is active (low). When RESET is de-asserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during powerdown, configure the programmable flag as an output when connected to a three-stated buffer. This ensures that the pin will be held at a constant level, and will not oscillate should the three-state driver's level hover around the logic switching point. Table 2 ADSP-2188M Modes of Operation
MODE D MODE C MODE B MODE A Booting Method BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.1 No Automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used but the processor does not automatically use or wait for these operations. BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. IACK has active pulldown. (REQUIRES ADDITIONAL HARDWARE). IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK has active pulldown.1 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode; IACK requires external pulldown. (REQUIRES ADDITIONAL HARDWARE). IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK requires external pulldown.1
X X
0 0
0 1
0 0
0
1
0
0
0 1
1 1
0 0
1 0
1
1
0
1
1. Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
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April 1999
Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be "wire OR'd". Mode D = 1 and in host mode: IACK is an open drain and requires an external pulldown, but multiple IACK pins can be "wire OR'd" together.
MEMORY ARCHITECTURE
The ADSP-2188M provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to the following figures and tables for PM and DM memory allocations in the ADSP-2188M.
Program Memory
Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2188M has 48K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces using the external data bus.
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Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in host mode due to a restricted data bus that is 16-bits wide only.
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Table 3 PMOVLAY bits
PMOVLAY 0, 4, 5, 6, 7 1 2 Memory Internal External Overlay 1 External Overlay 2 A13 Not Applicable 0 1 A12:0 Not Applicable 13 LSBs of Address Between 0x2000 and 0x3FFF 13 LSBs of Address Between 0x2000and 0x3FFF
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Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2188M has 56K words on Data Memory RAM on chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register and the waitstate mode bit.
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DMOVLAY 0, 4, 5, 6, 7, 8 1 2 Memory Internal External Overlay 1 External Overlay 2 A13 Not Applicable 0 1 A12:0 Not Applicable 13 LSBs of Address Between 0x2000 and0x3FFF 13 LSBs of Address Between 0x2000and 0x3FFF
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Memory Mapped Registers (New to the ADSP-2188M)
The ADSP-2188M has three memory mapped registers that differ from other ADSP-21xx Family DSPs. The slight modifications to these registers (Waitstate Control, Programmable Flag & Composite Select Control, and System Control) provide the ADSP-2188M's waitstate and BMS control features.
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Figure 6 Waitstate Control Register (ADSP-2188M)
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I/O Space (Full Memory Mode)
The ADSP-2188M supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAIT0-3, which in combination with the waitstate mode bit, specify up to 15 wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table 5. Table 5 Wait States
Address Range 0x000-0x1FF 0x200-0x3FF 0x400-0x5FF 0x600-0x7FF Wait State Register IOWAIT0 and Wait State Mode Select bit IOWAIT1 and Wait State Mode Select bit IOWAIT2 and Wait State Mode Select bit IOWAIT3 and Wait State Mode Select bit
Composite Memory Select (CMS)
The ADSP-2188M has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit. The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit.
Byte Memory Select (BMS)
The ADSP-2188M's BMS disable feature combined with the CMS pin lets you use multiple memories in the byte memory space. For example, an EPROM could be attached to the BMS select, and an SRAM could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting. After booting, software could disable BMS and set the CMS signal to respond to BMS, enabling the SRAM.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K x 8. The byte memory space on the ADSP-2188M supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits
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23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg x 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register and the waitstate mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred.
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Figure 9 BDMA Control Register The BDMA circuit supports four different data formats which are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table 6 shows the data formats supported by the BDMA circuit. Table 6 Data Formats
BTYPE 00 01 10 11 Internal Memory Space Program Memory Data Memory Data Memory Data Memory Word Size 24 16 8 8 Alignment Full Word Full Word MSBs LSBs
Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations.
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The source or destination of a BDMA transfer will always be on-chip program or data memory. When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor, and start execution at address 0 when the BDMA accesses have completed. The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory. The BMWAIT field, which has 4-bits on ADSP-2188M, lets you select up to 15 waitstates for BDMA transfers.
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
The IDMA Port provides an efficient means of communication between a host system and the ADSP2188M. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot be used, however, to write to the DSP's memory-mapped control registers. A typical IDMA transfer process is described as follows: 1. Host starts IDMA transfer 2. Host checks IACK control line to see if the DSP is busy 3. Host uses IS and IAL control lines to latch either the DMA starting address (IDMAA) or the PM/ DM OVLAY selection into the DSP's IDMA control registers. If bit 15 = 1, the value of bits 7:0 represent the IDMA overlay: bits 14:8 must be set to 0. If bit 15 = 0, the value of bits 13:0 represent the starting address of internal memory to be accessed and bit 14 reflects PM or DM for access. 4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM). 5. Host checks IACK line to see if the DSP has completed the previous IDMA operation. 6. Host ends IDMA transfer. The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-2188M is operating at full speed. The DSP memory address is latched and then is automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the IDMA address latch signal (IAL) or the missing edge of the IDMA select signal (IS) latches this value into the IDMAA register. Once the address is stored, data can then be either read from, or written to, the ADSP-2188M's onchip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2188M that a particular transaction is required. In either case, there is
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a one-processor-cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented, and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2188M to write the address onto the IAD0-14 bus into the IDMA Control Register. If bit 15 is set to 0, IDMA latches the address. If bit 15 is set to 1, IDMA latches into the OVLAY register.This register, shown below, is memory mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot be read back by the host. Refer to the following figures for more information on IDMA and DMA memory maps.
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Figure 10 IDMA Control/OVLAY Registers
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Bootstrap Loading (Booting)
The ADSP-2188M has two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting is controlled by the Mode A, B, and C configuration bits. When the MODE pins specify BDMA booting, the ADSP-2188M initiates a BDMA boot sequence when reset is released. The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD, and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24 bit words, and the BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP-2188M. The only memory address bit provided by the processor is A0.
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The ADSP-2188M can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-2188M boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to.
Bus Request & Bus Grant
The ADSP-2188M can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP2188M is not performing an external memory access, then it responds to the active BR input in the following processor cycle by:
* * *
Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, Asserting the bus grant (BG) signal, and Halting program execution.
If Go Mode is enabled, the ADSP-2188M will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2188M is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, re-enables the output drivers and continues program execution from the point where it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2188M requires the external bus for a memory or BDMA access, but is stopped. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2188M deasserts BG and BGH and executes the external memory access.
Flag I/O Pins
The ADSP-2188M has eight general purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2188M's clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, the ADSP-2188M has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1, and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT1. Note: Pins PF0, PF1, PF2 and PF3 are also used for device configuration during reset.
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Instruction Set Description
The ADSP-2188M assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor's unique architecture, offers the following benefits:
* * *
* *
The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP-2188M's interrupt vector and reset vector map. Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2188M has on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE's in-circuit probe, a 14-pin plug. Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including a reset of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. If you are using a passive method of maintaining mode information (as discussed in Setting Memory Modes) then it does not matter that the mode information is latched by an emulator reset. However, if you are using the RESET pin as a method of setting the value of the mode pins, then you have to take into consideration the effects of an emulator reset. One method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in Figure 12. This circuit forces the value located on the Mode A pin to logic high; regardless if it latched via the RESET or ERESET pin .
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Figure 12 Mode A Pin/EZ-ICE Circuit See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products.
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April 1999
ADSP-2188M Preliminary Data Sheet
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The ICE-Port interface consists of the following ADSP-2188M pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and ELOUT These ADSP-2188M pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-2188M and the connector must be kept as short as possible, no longer than 3 inches. The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2188M in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in Figure 13. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector.
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Target Memory Interface
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below.
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PM, DM, BM, IOM, & CM
Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in this data sheet. The performance of the EZICE may approach published worst case specification for some memory access timing requirements and switching characteristics. Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing requirements within published limits. Restriction: All memory strobe signals on the ADSP-2188M (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some system signals change. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board:
* * * * *
EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal. EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal. EZ-ICE emulation ignores RESET and BR when single- stepping. EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP's external memory bus only if bus grant (BG) is asserted by the EZICE board's DSP.
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April 1999
ADSP-2188M Preliminary Data Sheet
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ADSP-2188M-ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
Parameter K Grade Min VDDINT VDDEXT VINPUT1 TAMB 2.37 2.37 VIL = -0.3 0 Max 2.63 3.6 VIH = 3.6 +70 B Grade Min TBD TBD TBD -40 Max TBD TBD TBD +85 V V V C Unit
1. The ADSP-2188M is 3.3V tolerant (always accepts up to 3.6 Volt max VIH), but voltage compliance (on outputs, VOH) depends on the input V DDEXT; because VOH (max)VDDEXT (max). This applies to Bidirectional pins (D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD).
ELECTRICAL CHARACTERISTICS
K/B Grades Parameter V,+, Hi-Level Input Voltage1, 2 V,+, Hi-Level CLKIN Voltage V,/, Lo-Level Input Voltage1, 3 V2+, Hi-Level Output Voltage1, 4, 5 Test Conditions Min @ V'',17 = max @ V'',17 = max @ V'',17 = min @ V''(;7 = min, I2+ = -0.5 mA @ V''(;7 = 3.0V, I2+ = -0.5 mA @ V''(;7 = min, I2+ = -100 A6 V2/, Lo-Level Output Voltage1, 4, 5 I,+, Hi-Level Input Current3 I,/, Lo-Level Input Current3 @ V''(;7 = min, I2/ = 2 mA @ V'',17 = max, V,1 = 3.6V @ V'',17 = max, V,1 = 0 V 2.0 2.4 V''(;7-0.3 0.4 10 10 1.5 2.0 0.7 Typ Max V V V V V V V A A Unit
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ELECTRICAL CHARACTERISTICS (Continued)
K/B Grades Parameter I2=+, Three-State Leakage Current7 I2=/, Three-State Leakage Current7 I'', Supply Current (Idle)9 I'', Supply Current (Idle)9 I'', Supply Current (Dynamic)10 Test Conditions Min @ V''(;7 = max, V,1 = 3.6V8 @ VDDEXT = max, VIN = 0 V8 @ V'',17 = 2.5, t&. = 15 ns @ V'',17 = 2.5, t&. = 13.3 ns @ V'',17 = 2.5, t&. = 15 ns11, T$0%=+25C @ V'',17 = 2.5, t&. = 13.3 ns11, T$0%=+25C Lowest power mode @ V,1 = 2.5 V, f,1 = 1.0 MHz, T$0% = +25C @ V,1 = 2.5 V, f,1 = 1.0 MHz, T$0%=+25C TBD TBD TBD Typ Max 10 10 A A mA mA mA Unit
I'', Supply Current (Dynamic)10
TBD
mA
I'', Supply Current (Powerdown)12 C,, Input Pin Capacitance3, 6, 13
TBD 8
A pF
C2, Output Pin Capacitance6,7,12,14
8
pF
1. Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7. 2. Input only pins: RESET, BR, DR0, DR1, PWD. 3. Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4. Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH. 5. Although specified for TTL outputs, all ADSP-2188M outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no DC loads. 6. Guaranteed but not tested. 7. Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0-PF7. 8. 0 V on BR. 9. Idle refers to ADSP-2188M state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND. 10.IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11.VIN = 0 V and 3 V. For typical figures for supply currents, refer to "Power Dissipation" section. 12.See Chapter 9 of the ADSP-2100 Family User's Manual for details 13.Applies to LQFP package type. 14.Output pin capacitance is the capacitive load for any three-stated output pin.
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ADSP-2188M Preliminary Data Sheet
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ABSOLUTE MAXIMUM RATINGS1
Parameter Internal Supply Voltage (VDDINT) External Supply Voltage (VDDEXT) Input Voltage2 Output Voltage Swing3 Operating Temperature Range (Ambient) Storage Temperature Range Lead Temperature (5 sec) LQFP Value Min -0.3 V -0.3 V -0.5 V -0.5 V -40 C -65 C Max +3.0 V +4.6 V +4.6 V VDDEXT + 0.5 V +85 C +150 C +280 C
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Applies to Bidirectional pins (D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD). 3. Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH).
ESD SENSITIVITY
CAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2188M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADSP-2188M TIMING PARAMETERS GENERAL NOTES
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its signals. You have no control over this timing--circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.
MEMORY TIMING SPECIFICATIONS
The table below shows common memory device specifications and the corresponding ADSP-2188M timing parameters, for your convenience. Memory Device Specification Address setup to Write Start Address Setup to Write End Address Hold Time Data Setup Time Data Hold Time OE to Data Valid Address Access Time Parameter t$6: t$: t:5$ t': t'+ t5'' t$$ Timing Parameter Definition1 A0-A13, xMS Setup before WR Low A0-A13, xMS Setup before WR Deasserted A0-A13, xMS Hold before WR Low Data Setup before WR High Data Hold after WR High RD Low to Data Valid A0-A13, xMS to Data Valid
1. NOTE: xMS = PMS, DMS, BMS, CMS, or IOMS
FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS
tCK is defined as 0.5tCKI. The ADSP-2188M uses an input clock with a frequency equal to half the instruction rate: a 37.50 MHz input clock (which is equivalent to 26.7 ns) yields a 13.3 ns processor cycle (equivalent to 75 MHz). tCK values within the range of 0.5tCKI period should be substituted for all relevant timing parameters to obtain the specification value.
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April 1999
Example:
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t&.+ = 0.5t&. - 7 ns = 0.5 (15 ns) - 7 ns = 0.5 ns
ENVIRONMENTAL CONDITIONS1
Rating Description Thermal Resistance (Case-to-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case)
1. Where the Ambient Temperature Rating (TAMB) is: TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W
Symbol CA JA JC
Value 48 C/W 50 C/W 2 C/W
POWER DISSIPATION
To determine total power dissipation in a specific application, the following equation should be applied for each output: C x VDD2 x f C = load capacitance, f = output switching frequency. Example: In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions:
* * * *
External data memory is accessed every cycle with 50% of the address pins switching. External data memory writes occur every other cycle with 50% of the data pins switching. Each address and data pin has a 10 pF total load at the pin. The application operates at VDDEXT = 3.3 V and tCK = 15 ns.
Total Power Dissipation = PINT + (C x VDDEXT2 x f) PINT = internal power dissipation from Power vs. Frequency graph (Figure 15). (C x VDDEXT2 x f) is calculated for each output:
Parameters Address, DMS Data Output, WR RD CLKOUT # of Pins 8 9 1 1 xC 10 pF 10 pF 10 pF 10 pF x VDDEXT2 3.32 V 3.32 V 3.32 V 3.32 V xf 33.3 MHz 16.67 MHz 16.67 MHz 33.3 MHz PD 29.0 mW 16.3 mW 1.8 mW 3.6 mW 50.7 mW
Total power dissipation for this example is PINT + 50.7 mW.
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Output Drive Currents
Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2188M. The curves represent the current drive capability of the output drivers as a function of output voltage.
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April 1999
ADSP-2188M Preliminary Data Sheet
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Capacitive Loading
Figure 16 and Figure 17 show the capacitive loading characteristics of the ADSP-2188M.
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April 1999
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April 1999 TEST CONDITIONS Output Disable Time
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Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (t DIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: t DECAY = C L * 0.5V iL from which tDIS = tMEASURED - tDECAY is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving.
IN P U T
1 .5 V
2 .0 V O U T PU T 1 .5 V 0 .8 V
Figure 18 Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
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Output Enable Time
Output pins are considered to be enabled when that have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving
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Figure 19 Output Enable/Disable
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Figure 20 Equivalent Device Loading for AC Measurements (Including All Fixtures)
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April 1999 TIMING PARAMETERS ADSP-2188M Clock Signals and Reset
Parameter
Clock Signals and Reset Timing Requirements: tCKI CLKIN Period tCKIL CLKIN Width Low tCKIH CLKIN Width High Switching Characteristics: tCKL CLKOUT Width Low tCKH CLKOUT Width High tCKOH CLKIN High to CLKOUT High Control Signals Timing Requirements: tRSP RESET Width Low tMS Mode Setup Before RESET High Mode Hold After RESET High tMH
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Min
26.6 13 13 0.5tCK - 2 0.5tCK - 2 0
Max
100
Unit
ns ns ns ns ns ns
13
5tCK1 2 5
ns ns ns
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time)
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Figure 21 Clock Signals
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TIMING PARAMETERS ADSP-2188M Interrupts and Flags
3DUDPHWHU Interrupts and Flag Timing Requirements: IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 tIFS tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 Switching Characteristics: tFOH Flag Output Hold after CLKOUT Low5 tFOD Flag Output Delay from CLKOUT Low 5 0LQ 0D[ 8QLW
0.25tCK + 10 0.25tCK 0.5tCK - 5
ns ns ns ns
0.5tCK + 4
NOTES 1If IRQx and FI inputs meet t IFS and t IFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to Interrupt Controller Operation" in the Program Control chapter of the ADSP2100 Family User's Manual for further information on interrupt servicing.) 2Edge-sensitive interrupts require pulse widths greater than 10ns; level-sensitive interrupts must be held low until serviced. 3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE. 4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5Flag Outputs = PFx, FL0, FL1, FL2, Flag_out.
W ) 2'
&/.2 8 7
W ) 2+
)/ $* 2 87 38 76
W,) +
,5 4 [ ), 3) [
W ,) 6
Figure 22 Interrupts and Flags
REV. PrA
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39
April 1999 TIMING PARAMETERS ADSP-2188M Bus Request-Bus Grant
3DUDPHWHU Bus Request/Grant Timing Requirements: tBH BR Hold after CLKOUT High1 tBS BR Setup before CLKOUT Low1 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable tSDB xMS, RD, WR Disable to BG Low tSE BG High to xMS, RD, WR Enable tSEC xMS, RD, WR Enable to CLKOUT High tSDBH xMS, RD, WR Disable to BGH Low2 tSEH BGH High to xMS, RD, WR Enable2
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
0LQ 0.25tCK + 2 0.25tCK + 10
0D[
8QLW ns ns
0 0 0.25tCK - 3 0 0
0.25tCK + 8
ns ns ns ns ns ns
NOTES xMS = PMS, DMS, CMS, IOMS, BMS 1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User's Manual for BR/BG cycle relationships. 2BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
tB H
CLKOUT
%5
tB S
CLKOUT
30 6 n ' 0 6 %0 6n 5' :5 %*
tS D
tS E C
tS D B tS E
%* +
tSD B H
tS E H
Figure 23 Bus Request-Bus Grant
40
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REV. PrA
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
TIMING PARAMETERS ADSP-2188M Memory Read
3DUDPHWHU Memory Read Timing Requirements: tRDD RD Low to Data Valid tAA A0-A13, xMS to Data Valid tRDH Data Hold from RD High Switching Characteristics: tRP RD Pulse Width tCRD CLKOUT High to RD Low tASR A0-A13, xMS Setup before RD Low tRDA A0-A13, xMS Hold after RD Deasserted tRWR RD High to RD or WR Low w = wait states x tCK xMS = PMS, DMS, CMS, IOMS, BMS 0LQ 0D[ 0.5tCK - 5 + w 0.75t CK - 6 + w 8QLW ns ns ns ns ns ns ns ns
0 0.5tCK - 3 + w 0.25tCK - 2 0.25tCK - 3 0.25tCK - 3 0.5tCK - 3
0.25tCK + 4
&/.287
$i $ie
'0 6n 30 6n %0 6n ,2 0 6n &0 6
tR D A
5'
t A SR tC R D
'
tR P
tR W R
tR D D tA A
:5
tR D H
Figure 24 Memory Read
REV. PrA
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41
April 1999 TIMING PARAMETERS ADSP-2188M Memory Write
3DUDPHWHU Memory Write Switching Characteristics: tDW Data Setup before WR High tDH Data Hold after WR High tWP WR Pulse Width tWDE WR Low to Data Enabled tASW A0-A13, xMS Setup before WR Low tDDR Data Disable before WR or RD Low tCWR CLKOUT High to WR Low tAW A0-A13, xMS, Setup before WR Deasserted tWRA A0-A13, xMS Hold after WR Deasserted tWWR WR High to RD or WR Low w = wait states x tCK xMS = PMS, DMS, CMS, IOMS, BMS
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
0LQ 0.5tCK - 4+ w 0.25tCK - 1 0.5tCK - 3 + w 0 0.25tCK - 3 0.25tCK - 3 0.25tCK - 2 0.75tCK - 5 + w 0.25tCK - 1 0.5tCK - 3
0D[
8QLW ns ns ns ns ns ns ns ns ns ns
0.25 tCK + 4
CLKOUT
A 0-A 1 3
'0 6n 30 6n %0 6n & 0 6 n ,2 0 6
tW R A
:5
tA S W tA W tC W R
D
tW P tD H
tW W R tD D R
tD W tW D E
5'
Figure 25 Memory Write
42
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrA
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
TIMING PARAMETERS ADSP-2188MSerial Ports
3DUDPHWHU Serial Ports Timing Requirements: tSCK SCLK Period tSCS DR/TFS/RFS Setup before SCLK Low tSCH DR/TFS/RFS Hold after SCLK Low tSCP SCLKIN Width Switching Characteristics: tCC CLKOUT High to SCLKOUT tSCDE SCLK High to DT Enable tSCDV SCLK High to DT Valid tRH TFS/RFSOUT Hold after SCLK High tRD TFS/RFSOUT Delay from SCLK High tSCDH DT Hold after SCLK High tTDE TFS (Alt) to DT Enable tTDV TFS (Alt) to DT Valid tSCDD SCLK High to DT Disable tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 0LQ 26.67 4 7 12 0.25tCK 0 0 12 0 0 12 12 12 0.25tCK + 6 12 0D[ 8QLW ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CLKOUT
tC C
tC C
tS C K
SCLK
tS C P tS C S tS C H tS C P
'5 7) 6 ,1 5)6 ,1
tR D tR H
5)6 2 8 7 7)6 28 7
tS C D D tS C D V tS C D E tS C D H
DT
tT D E tT D V
T F S 2 87
ALT ER NATE FRA M E M OD E
tR D V
RF S O UT
M U L T IC H A N N E L MOD E, FR A M E DELA Y 0 (M F D = 0 )
tT D E tT D V
T F S IN
ALT ER NATE FRA M E M OD E
tR D V
RF S IN
M U L T IC H A N N E L MODE, FR A M E DEL A Y 0 (M F D = 0 )
Figure 26 Serial Ports
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43
April 1999 TIMING PARAMETERS ADSP-2188M IDMA Address Latch
3DUDPHWHU IDMA Address Latch Timing Requirements: tIALP Duration of Address Latch 1, 3 tIASU IAD15-0 Address Setup before Address Latch End 3 tIAH IAD15-0 Address Hold after Address Latch End3 tIKA IACK Low before Start of Address Latch2, 3 tIALS Start of Write or Read after Address Latch End2, 3 tIALD Address Latch Start after Address Latch End1, 3 NOTES 1Start of Address Latch = IS Low and IAL High. 2Start of Write or Read = IS Low and IWR Low or IRD Low. 3End of Address Latch = IS High or IAL Low.
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
0LQ 10 5 2 0 3 TBD
0D[
8QLW ns ns ns ns ns ns
,$ & .
W ,. $
,$ /
W ,$ /'
W ,$ / 3
,6
W ,$ /3
,$ ' i e i
W ,$ 6 8
W,$ +
W ,$ 6 8
W ,$ + W ,$ / 6
,5' 2 5 ,:5
Figure 27 IDMA Address Latch
44
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
TIMING PARAMETERS ADSP-2188M IDMA Write, Short Write Cycle
3DUDPHWHU IDMA Write, Short Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 tIWP Duration of Write1, 2 tIDSU IAD15-0 Data Setup before End of Write2, 3, 4 tIDH IAD15-0 Data Hold after End of Write2, 3, 4 Switching Characteristics: tIKHW Start of Write to IACK High NOTES 1Start of Write = IS Low and IWR Low. 2End of Write = IS High or IWR High. 3If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 4If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. 0LQ 0 10 3 2 10 0D[ 8QLW ns ns ns ns ns
t ,. :
,$ & .
t ,. + :
,6
t ,: 3
,: 5
t ,' + t ,' 6 8
IA D 1 5 -0 D AT A
Figure 28 IDMA Write, Short Write Cycle
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
45
April 1999 TIMING PARAMETERS ADSP-2188M IDMA Write, Long Write Cycle
3DUDPHWHU IDMA Write, Long Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 tIKSU IAD15-0 Data Setup before End of Write2, 3, 4 tIKH IAD15-0 Data Hold after End of Write2, 3, 4 Switching Characteristics: tIKLW Start of Write to IACK Low4 tIKHW Start of Write to IACK High
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
0LQ 0 .5t&. + 5 0 1.5tCK
0D[
8QLW ns ns ns ns ns
10
NOTES 1Start of Write = IS Low and IWR Low. 2If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 3If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. 4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User's Manual.
,$&.
W ,.$
,$/
W,$/'
W ,$/3
,6
W ,$/3
,$' iei
W,$68
W,$+
W,$68
W,$+ W ,$/6
,5' 2 5 ,:5
Figure 29 IDMA Write, Long Write Cycle
46
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrA
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
TIMING PARAMETERS ADSP-2188M IDMA Read, Long Read Cycle
3DUDPHWHU IDMA Read, Long Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 Switching Characteristics: tIKHR IACK High after Start of Read1 tIKDS IAD15-0 Data Setup before IACK Low tIKDH IAD15-0 Data Hold after End of Read2 tIKDD IAD15-0 Data Disabled after End of Read2 tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read tIRDH1 IAD15-0 Previous Data Hold after Start of Read (DM/PM1)3 tIRDH2 IAD15-0 Previous Data Hold after Start of Read (PM2)4 NOTES 1Start of Read = IS Low and IRD Low. 2End of Read = IS High or IRD High. 3DM read or first half of PM read. 4Second half of PM read. 0LQ 0 10 0.5tCK - 2 0 10 0 10 2tCK - 5 tCK - 5 0D[ 8QLW ns ns ns ns ns ns ns ns ns
,$ & .
tI K H R tI K R
,6
tI R P
,5 '
tI R D E
PR E V IO U S D AT A
tI K D S
RE A D D AT A
tI K D H
IA D 1 5 -0
tI R D V tI R D H
tI K D D
Figure 30 IDMA Read, Long Read Cycle
REV. PrA
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47
April 1999 TIMING PARAMETERS ADSP-2188M IDMA Read, Short Read Cycle
3DUDPHWHU IDMA Read, Short Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 tIRP Duration of Read Switching Characteristics: tIKHR IACK High after Start of Read1 tIKDH IAD15-0 Data Hold after End of Read2 tIKDD IAD15-0 Data Disabled after End of Read2 tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read NOTES 1Start of Read = IS Low and IRD Low. 2End of Read = IS High or IRD High.
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
0LQ0D[ 0 10 10 0 10 0 10
8QLW ns ns ns ns ns ns ns ns
,$ & .
tI K R tI K H R
,6
,5 '
tI R P
tI R D E
PR E V IO U S D AT A
tI K D H
IA D 1 5 -0
tI R D V
tI K D D
Figure 31 IDMA Read, Short Read Cycle
48
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REV. PrA
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
100-Lead LQFP Package Pinout
i $ e i ,$ ' e $ e i ,$ ' e *1' $ c i ,$ ' e $ aei ,$ ' c $ a i ,$ ' ae $ a i ,$ ' a $ ii i ,$ ' a $ ii i ,$ ' ii $ ie i ,$ ' ii $ ie i ,$ ' ie *1' & /. ,1 ; 7$ / 9 ' ' (; 7 & /. 2 8 7 *1' 9 ' ' ,17 :5 5' %0 6 '06 30 6 ,2 0 6 &06 ee
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,5 4 /i n 3 )e
,5 4 ( n 3 )e
*1'
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49
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
The ADSP-2188M package pinout appears in Table 7. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. Table 7 ADSP-2188M Package Pinout
LQFP Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name A4 / IAD3 A5 / IAD4 GND A6 / IAD5 A7 / IAD6 A8 / IAD7 A9 / IAD8 A10 / IAD9 A11 / IAD10 A12 / IAD11 A13 / IAD12 GND CLKIN XTAL VDDEXT CLKOUT GND VDDINT WR RD BMS DMS PMS IOMS CMS LQFP Number 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Pin Name IRQE + PF4 IRQL0 + PF5 GND IRQL1 + PF6 IRQ2 + PF7 DT0 TFS0 RFS0 DR0 SCLK0 VDDEXT DT1 TFS1 RFS1 DR1 GND LQFP Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Pin Name EBR BR EBG BG D0 / IAD13 D1 / IAD14 D2 / IAD15 D3 / IACK VDDINT GND D4 / IS D5 / IAL D6 / IRD D7 / IWR D8 GND LQFP Number 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Pin Name D16 D17 D18 D19 GND D20 D21 D22 D23 FL2 FL1 FL0 PF3 [Mode D] PF2 [Mode C] VDDEXT PWD GND PF1 [Mode B] PF0 [Mode A] BGH PWDACK A0 A1/IAD0 A2 / IAD1 A3 / IAD2
Y R A IN AL IM IC LN EH RC A PE T T DA
42 SCLK1 67 VDDEXT 92 43 ERESET 68 69 70 D9 93 94 95 44 45 46 47 48 49 50 RESET EMS EE D10 D11 71 72 73 74 GND D12 D13 D14 96 97 98 99 ECLK ELOUT ELIN EINT 75 D15 100
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50
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
OUTLINE DIMENSIONS
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Figure 32 100-Lead Metric Thin Plastic Quad Flatpack (Dimensions shown in millimeters and inches)
ORDERING GUIDE
Part Number ADSP-2188MKST-300x Ambient Temperature Range 0C to +70C Instruction Rate 75 Package Description1 100-Lead LQFP Package Option ST-100
1. In 1998, JEDEC re-evaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labelled TQFP packages (1.6 mm thick) are now designated as LQFP.
PRINTED IN USA
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51
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
April 1999
REV. PrA
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